1. Field of the Invention
The present invention relates to a timing circuit, and in particular to one that is an improvement upon a timing circuit connected to a comparator circuit output.
2. Description of the Prior Art
In prior art timing circuits connected to the output of an operational amplifier comparator circuit, as shown in FIG. 1 of the drawings, a standard circuit has been used wherein a resistor RL and a capacitor CO are connected to the output of a comparator amplifier Y1 and determine the output time constant of the amplifier Y1 appearing at output terminal 3. The potential of terminals 1 and 1' is a reference or ground potential. Supply sources to Y1 are V.sup.+ and V.sup.-. Resistor R.sub.f is a feedback resistor, and RO is an output load resistor. A potential corresponding to a signal level is applied at terminal 2 and is compared to the reference potential and inverted by amplifier Y1.
When a voltage higher than the reference potential is applied at terminal 2, where RL &lt;&lt; RO and the output resistance of Y1 is sufficiently small, the output voltage at the output of Y1 swings sharply negative and the voltage at terminal 3 changes from the reference potential to V.sup.- potential with the time constant of T.sub.O =R.sub.L.sup.19 C.sub.O. Next, when the applied voltage at terminal 2 is removed, the output of Y1 returns sharply to the reference voltage and that of terminal 3 returns to the reference potential with the same time constant, T.sub.O. Conversely, when a voltage lower than the reference potential is applied at terminal 2, the output potential of Y1 swings sharply positive and that of terminal 3 shifts to potential V.sup.+ at the same time constant, T.sub.O. Then, when the input at terminal 2 is removed, the voltage at terminal 3 returns to the reference voltage at the same time constant, T.sub.O.
Recently there has developed a need for timing circuits connected to the output of a comparator amplifier which can respond with a short "attack" time constant to the application of a voltage pulse of either polarity to the comparator input and which can respond with a long "release" time constant to the removal of said voltage pulse from the comparator input, (that is, the return of the output to reference potential), and which has different attack time constants corresponding to the polarity of the comparator output with respect to the reference voltage. Prior art timing circuits have a disadvantage in only being able to respond with a single time constant, whether the pulse is being applied or removed, and without regard for the polarity of the output potential of the comparator as described above.
A primary object of this invention is to provide a timing circuit which responds with different time constants depending on whether a pulse is being applied or being removed at the input of a comparator amplifier.
A further object of this invention is to provide a timing circuit which can respond with different time constants to pulses of different polarity applied at the input of a comparator amplifier.